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Flash Memory IC Chip MT47H16M16BG-3 IT:B TR - Micron Technology - DDR2 SDRAM

Flash Memory IC Chip MT47H16M16BG-3 IT:B TR - Micron Technology - DDR2 SDRAM

Categories Flash Memory IC Chip
Package: FBGA
Place of Origin: PHILIPPINE
Brand Name: Micron Technology
Certification: Lead free / RoHS Compliant
Model Number: MT47H16M16BG-3 IT:B TR
MOQ: 50
Price: Contact for Sample
Packaging Details: Contact for Sample
Delivery Time: Within 3days
Payment Terms: T/T in advance, Paypal, Western Union
Supply Ability: 5000
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    Flash Memory IC Chip MT47H16M16BG-3 IT:B TR - Micron Technology - DDR2 SDRAM

    Quick Detail:


    DDR2 SDRAM


    Description:


    The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

    A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,UDQS#).

    The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK.

    Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to selectthe bank and the starting column location for the burst access.

    The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

    As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time.

    A self refresh mode is provided, along with a power-saving, power-down mode.

    All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.


    Applications:


    VDD = 1.8V ±0.1V, V DDQ = 1.8V ±0.1V

    JEDEC-standard 1.8V I/O (SSTL_18-compatible)

    Differential data strobe (DQS, DQS#) option

    4n-bit prefetch architecture

    Duplicate output strobe (RDQS) option for x8

    DLL to align DQ and DQS transitions with CK

    4 internal banks for concurrent operation

    Programmable CAS latency (CL)

    Posted CAS additive latency (AL)

    WRITE latency = READ latency - 1 tCK

    Selectable burst lengths (BL): 4 or 8

    Adjustable data-output drive strength

    64ms, 8192-cycle refresh

    On-die termination (ODT)

    Industrial temperature (IT) option

    Automotive temperature (AT) option

    RoHS-compliant

    Supports JEDEC clock jitter specification


    Specifications:

    Datasheets

    MT47H64M4,32M8,16M16

    Product Photos

    84 FBGA Package

    Standard Package

    1,000

    Category

    Integrated Circuits (ICs)

    Family

    Memory

    Series

    -

    Packaging

    Tape & Reel (TR)

    Format - Memory

    RAM

    Memory Type

    DDR2 SDRAM

    Memory Size

    256M (16Mx16)

    Speed

    3ns

    Interface

    Parallel

    Voltage - Supply

    1.7 V ~ 1.9 V

    Operating Temperature

    -40°C ~ 95°C

    Package / Case

    84-FBGA

    Supplier Device Package

    84-FBGA (8x14)


    Competitive Advantage:


    warranty :180days for all goods

    Free shipping:Order over $600 win a free shipment fee:goods weight below 3Kg.

    Mega Source Electronics stocks components ready to ship. Hard to find, obsolete and highly allocated integrated circuits and semiconductors are all can be found by us.

    Mega Source Electronics has established a well-developed logistics system and global logistics network, which can guarantee our service very quick, convenient and efficient.

    Quality Flash Memory IC Chip MT47H16M16BG-3 IT:B TR - Micron Technology - DDR2 SDRAM for sale
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